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1 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V fuji power supply control ic FA3687V application note may ?2001 fuji electric co., ltd. matsumoto factory
2 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V 1.this data book contains the product specifications, characteristics, data, materials, and structures as of may 2001. the contents are subject to change without notice for specification changes or other reasons. when using a product listed in this data book, be sure to obtain the latest specifications. 2. all applications described in this data book exemplify the use of fuji's products for your reference only. no right or license, either express or implied, under any patent, copyright, trade secret or other intellectual property right owned by fuji electric co., ltd. is (or shall be deemed) granted. fuji makes no representation or warranty, whether express or implied, relating to the infringement or alleged infringement of other's intellectual property rights, which may arise from the use of the applications, described herein. 3. although fuji electric is enhancing product quality and reliability, a small percentage of semiconductor products may become faulty. when using fuji electric semiconductor products in your equipment, you are requested to take adequate safety measures to prevent the equipment from causing a physical injury, fire, or other problem if any of the products become faulty. it is recommended to make your design fail-safe, flame retardant, and free of malfunction. 4.the products introduced in this data book are intended for use in the following electronic and electrical equipment, which has normal reliability requirements. ? computers ? oa equipment ? communications equipment (pin devices) ? measurement equipment ? machine tools ? audiovisual equipment ? electrical home appliances ? personal equipment ? industrial robots etc. 5.if you need to use a product in this data book for equipment requiring higher reliability than normal, such as for the equipment listed below, it is imperative to contact fuji electric to obtain prior approval. when using these products for such equipment, take adequate measures such as a backup system to prevent the equipment from malfunctioning even if a fuji's product incorporated in the equipment becomes faulty. ? transportation equipment (mounted on cars and ships) ? trunk communications equipment ? traffic-signal control equipment ? gas leakage detectors with an auto-shut-off feature ? emergency equipment for responding to disasters and anti-burglary devices ? safety devices 6. do not use products in this data book for the equipment requiring strict reliability such as (without limitation) ? space equipment ? aeronautic equipment ? atomic control equipment ? submarine repeater equipment ? medical equipment 7. copyright ? 1995 by fuji electric co., ltd. all rights reserved. no part of this data book may be reproduced in any form or by any means without the express permission of fuji electric. 8. if you have any question about any portion in this data book, ask fuji electric or its sales agents before using the product. neither fuji nor its agents shall be liable for any injury caused by any use of the products not in accordance with instructions set forth herein. warning
3 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V contents page 1. description ??????????????????? 4 2. features ??????????????????? 4 3. outline ??????????????????? 4 4. block diagram ??????????????????? 5 5. pin assignment ??????????????????? 5 6. ratings and characteristics ??????????????????? 6 7. characteristic curves ??????????????????? 10 8. description of each circuit ??????????????????? 17 9. design advice ??????????????????? 21 10. application circuit ??????????????????? 25 note ? parts tolerance and characteristics are not defined in all application described in this data book. when design an actual circuit for a product, you must determine parts tolerances and characteristics for safe and stable operation.
4 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V 1. description FA3687V is a pwm type dc-to-dc converter control ic with 2ch outputs that can directly drive power mosfets. cmos devices with high breakdown voltage are used in this ic and low power consumption is achieved. this ic is suitable for very small dc-to-dc converters because of their small and thin package (1.1mm max.), and high frequency operation (to 1.5mhz). you can select pch or nch of mosfets driven, and design any topology of dc-to- dc converter circuit like a buck, a boost, a inverting, a fly-back, or a forward. 2. features ? ? wide range of supply voltage: v cc =2.5 to 20v ? ? mosfet direct driving ? ? selectable output stage for pch/nch mosfet on each channel ? ? low operating current by cmos process: 2.5ma (typ.) ? ? 2ch pwm control ic ? ? high frequency operation: 300khz to 1.5mhz ? ? simple setting of operation frequency by timing resistor ? ? soft start function at each channel ? ? adjustable maximum duty cycle at each channel ? ? built-in undervoltage lockout ? ? high accuracy reference voltage: v ref : 1.00v 1%, v reg : 2.20v 1% ? ? adjustable built-in timer latch for short-circuit protection ? ? thin and small package: tssop-16 3. outline
5 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V 4. block diagram 5. pin assignment pin no. pin symbol description 1 cp timer latched short circuit protection 2 sel2 selection of type of driven mosfet (out2) 3 fb2 ch.2 output of error amplifier 4 in2- ch.2 inverting input to error amplifier 5 in2+ ch.2 non-inverting input to error amplifier 6 vcc power supply 7 cs2 soft start for ch.2 8 out2 ch.2 output 9 out1 ch.1 output 10 cs1 soft start for ch.1 11 gnd ground 12 rt oscillator timing resistor 13 vreg regulated voltage output 14 in1- ch.1 inverting input to error amplifier 15 fb1 ch.1 output of error amplifier 16 sel1 selection of type of driven mosfet (out1) ,-,9,5*, ,-,9,5*, ,-,9,5*, ,-,9,5*, =63;(., =63;(., =63;(., =63;(., ,.<3(;,+ ,.<3(;,+ ,.<3(;,+ ,.<3(;,+ =63;(., =63;(., =63;(., =63;(., :*033(;69 :*033(;69 :*033(;69 :*033(;69 *+!$ *+!$ *+!$ *+!$ 6-; 6-; 6-; 6-; :;(9; :;(9; :;(9; :;(9; 04,9 04,9 04,9 04,9 3(;*/ 3(;*/ 3(;*/ 3(;*/ 9?47?? 9?47?? 9?47?? 9?47?? 9?47? 9?47? 9?47? 9?47?
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647? ?=63;(., ?=63;(., ?=63;(., ?=63;(., +,;,*;065 +,;,*;065 +,;,*;065 +,;,*;065 ??*/? ??*/? ??*/? ??*/? +90=, +90=, +90=, +90=, ? ? ? ? cc cc cc cc cs2 cs2 cs2 cs2 cs 1 cs 1 cs 1 cs 1 out 1 out 1 out 1 out 1 out2 out2 out2 out2 ? sel 1 ? sel 1 ? sel 1 ? sel 1 sel2 sel2 sel2 sel2 ? gnd ? gnd ? gnd ? gnd cp cp cp cp ? in 1 - ? in 1 - ? in 1 - ? in 1 - ? fb 1 ? fb 1 ? fb 1 ? fb 1 in2- in2- in2- in2- fb2 fb2 fb2 fb2 in2+ in2+ in2+ in2+ ? rt ? rt ? rt ? rt ?? ?? ?? ?? ? ? ? ? ??*/? ??*/? ??*/? ??*/? +90=, +90=, +90=, +90=,
6 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V 6. ratings and characteristics (1) absolute maximum ratings item symbol test condition rating unit power supply voltage v cc 20 v sel1 ? sel2 pin voltage v sel -0.3 to 5.0 v fb1 ? in1- ? fb2 ? in2- ? in2+ pin voltage v ea_in -0.3 to 5.0 v cs1 ? cs2 ? cp ? rt ? vreg pin voltage v ctr_in -0.3 to 5.0 v i out- -400(peak) ma out1/2 out pin source current out pin sink current i out+ 150(peak) ma i out- -50(continuous) ma out1/2 out pin source current out pin sink current i out+ 50(continuous) ma power dissipation 1 p d ta Q 25 300 mw operating junction temperature t j +125 operating ambient temperature t opr -30 to +85 storage temperature t stg -40 to +125 t ? 1 derating factor ta R 25 : 3mw/ (2) recommended operating conditions item symbol test condition min. typ. max. unit supply voltage v cc 2.5 \ 18 v cs1 ? cs2 ? cp pin voltage v ctr_in 0.0 \ 2.5 v sel1 ? sel2 pin voltage v sel_in 0.0 - 2.5 v in1- ? in2- ? in2+ pin voltage v ea_in 0.0 \ 2.5 v oscillation frequency f osc 300 500 1500 khz vcc 10v 0.1 1.0 4.7 f vreg pin capacitance c reg 10v Q vcc 18v 0.47 1.0 4.7 f vreg pin current i reg \\ 1.0 ma vcc pin capacitance c vcc 1.0 \\ f cs1 pin capacitance c cs1 between cs1 and gnd 0.01 \\ f cs2 pin capacitance c cs2 between cs2 and vreg 0.01 \\ f cp pin capacitance c cp between cp and vreg 2 D D ? 2. if the timer latched mode is not needed, connect the cp pin to gnd. maximum power dissipation curve 0 50 100 150 200 250 300 350 -30 0 30 60 90 120 150 ambient temperature [ ] maximun power dissipation [mw
7 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V (3) electrical characteristics * the characteristics is based on the condition of v cc =3.3v, c reg =1.0 f, r t =12k , ta=+25 , unless otherwise specified. (1) regulated voltage for internal control blocks (vreg pin) item symbol test condition min. typ. max. unit regulated voltage v reg 2.178 2.200 2.222 v line regulation v reg_line v cc =2.5 to 18v D 5 15 mv load regulation v reg_load i reg =0 to 1ma -5 -1 mv variation with temperature v reg_tc ta=-30 to +85 0.5 % (2) oscillator section (rt pin) item symbol test condition min. typ. max. unit oscillation frequency f osc 435 500 565 khz line regulation f osc_line v cc =2.5 to 18v D 1 5 % variation with temperature f osc_tc1 ta=-30 to +85 3 % (3) error amplifier section (in1- ? fb1 ? in2- ? in2+ ? fb2 pin) item symbol test condition min. typ. max. unit reference voltage (ch.1) v ref1 3 0.99 1.00 1.01 v v ref1 line regulation (ch.1) v ref_line v cc =2.5 to 18v D 2 5 mv v ref1 variation with temperature (ch.1) v ref_tc1 ta=-30 to +85 0.5 % input offset voltage (ch.2) v offset v in2+ =1.0v in2+ ? in2- DD 10 v offset line regulation (ch.2) v off_line v cc =2.5 18v 0 input bias current i in- v inx- =0.0 to 2.5v 0.0 ma common mode input voltage v com in2+ ? in2- 0.7 1.5 open loop gain a vo 70 db unity gain bandwidth f t 1.5 mhz output current (sink) i sifb v fb1 =0.5v,v in1- =v reg v fb2 =0.5v,v in2- =v reg ,v in2+ =1v 2.3 3.5 4.7 ma output current (source) i sofb v fb1 =v reg -0.5v,v in1 -=0v v fb2 =v reg -0.5v,v in2- =0v,v in2+ =1v -360 -270 -180 a * 3: the fb1 voltage is measured under the condition that in1- pin and fb1 pin are shorted. the input offset voltage of the error amplifier is included.
8 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V (4) soft start section (cs1 ? cs2 pin) item symbol test condition min. typ. max. unit v cs1d0n duty cycle=0%, v fb1 =1.4v 0.82 v cs1d20n duty cycle =20%, v fb1 =1.4v 0.89 0.925 0.96 v cs1d80n duty cycle =80%, v fb1 =1.4v 1.25 1.285 1.32 threshold voltage (cs1) (driving nch-mosfet) v cs1d100n duty cycle =100%, v fb1 =1.4v 1.38 v cs1d0p duty cycle =0%, v fb1 =1.4v 0.82 v cs1d20p duty cycle =20%, v fb1 =1.4v 0.90 0.935 0.97 v cs1d80p duty cycle =80%, v fb1 =1.4v 1.26 1.295 1.33 threshold voltage (cs1) (driving pch-mosfet) v cs1d100p duty cycle =100%, v fb1 =1.4v 1.38 v cs2d0n duty cycle =0%, v fb2 =0.7v 1.33 v cs2d20n duty cycle =20%, v fb2 =0.7v 1.21 1.245 1.28 v cs2d80n duty cycle =80%, v fb2 =0.7v 0.85 0.885 0.92 threshold voltage (cs2) (driving nch-mosfet) v cs2d100n duty cycle =100%, v fb2 =0.7v 0.80 v cs2d0p duty cycle =0%, v fb2 =0.7v 1.33 v cs2d20p duty cycle =20%, v fb2 =0.7v 1.20 1.235 1.27 v cs2d80p duty cycle =80%, v fb2 =0.7v 0.84 0.875 0.91 threshold voltage (cs2) (driving pch-mosfet) v cs2d100p duty cycle =100%, v fb2 =0.7v 0.80 (5) pulse width modulation (pwm) section (fb1 ? fb2 pin) item symbol test condition min. typ. max. unit v fb1d0n duty cycle =0%, v cs1 =v reg 0.82 v fb1d20n duty cycle =20%, v cs1 =v reg 0.925 v fb1d80n duty cycle =80%, v cs1 =v reg 1.285 threshold voltage (fb1) (driving nch-mosfet) v fb1d100n duty cycle =100%, v cs1 =v reg 1.38 v fb1d0p duty cycle =0%, v cs1 =v reg 0.82 v fb1d20p duty cycle =20%, v cs1 =v reg 0.935 v fb1d80p duty cycle =80%, v cs1 =v reg 1.295 threshold voltage (fb1) (driving pch-mosfet) v fb1d100p duty cycle =100%, v cs1 =v reg 1.38 v fb2d0n duty cycle =0%, v cs2 =0v 1.33 v fb2d20n duty cycle =20%, v cs2 =0v 1.245 v fb2d80n duty cycle =80%, v cs2 =0v 0.885 threshold voltage (fb2) (driving nch-mosfet) v fb2d100n duty cycle =100%, v cs2 =0v 0.80 v fb2d0p duty cycle =0%, v cs2 =0v 1.33 v fb2d20p duty cycle =20%, v cs2 =0v 1.235 v fb2d80p duty cycle =80%, v cs2 =0v 0.875 threshold voltage (fb2) (driving pch-mosfet) v fb2d100p duty cycle =100%, v cs2 =0v 0.80
9 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V (6) timer latch protection section (cp pin) item symbol test condition min. typ. max. unit threshold voltage of fb1 v thfb1tl 6-1 1.5 D 2.0 v threshold voltage of fb2 v thfb2tl 6-2 0.2 D 0.6 v threshold voltage of cs1 v thfb3tl 6-3 0.2 D 0.6 v threshold voltage of cs2 v vthcs1tl 6-4 1.5 D 2.0 v charge current of cp i cp v cp =0.5v,v fb1 =2.1v -2.4 -2.0 -1.5 a threshold voltage of cp v thcptl 1.6 D 2.1 v (7) under voltage lockout circuit section (vcc pin) item symbol test condition min. typ. max. unit on threshold voltage of vcc v uvlo 2.0 2.2 2.35 v hysteresis voltage v uvlo 0.1 v (8) output section (out1 ? out2 ? sel1 ? sel2 pin) item symbol test condition min. typ. max. unit i out2 =-50ma 10 20 i out1 =-50ma,v cc =5v 9 high side on resistance of out1/2 r onhi i out1 =-50ma,v cc =15v 8 i out1 =50ma 5 10 i out2 =50ma,v cc =5v 5 low side on resistance of out1/2 r onlo i out2 =50ma,v cc =15v 5 rise time of out1/2 t rise c l =1000pf 25 ns fall time of out1/2 t fall c l =1000pf 40 ns sel pin voltage for driving nch-mosfet v seln 0.0 D 0.2 sel pin voltage for driving pch-mosfet v selp v reg -0.2 D v reg (9) overall section item symbol test condition min. typ. max. unit i cca ch.1, ch.2 operating mode 2.5 3.5 ma i cca1 ch.1, ch.2 off mode 2.0 ma i cca2 ch.1, ch.2 operating mode, vcc=18v 3.0 ma operating mode supply current i cca3 latch mode 2.0 ma *6-1: the current source of the cp pin operates when the voltage of fb1 exceeds the threshold voltage as shown in the table. *6-2: the current source of the cp pin operates when the voltage of fb2 falls below the threshold voltage as shown in the table. * 6-3: the timer latch of fb1 is disabled when the cs1 voltage is below the threshold voltage as shown in the table. * 6-4: the timer latch of fb2 is disabled when the cs2 voltage is above the threshold voltage as shown in the table.
10 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V 7. characteristic curves oscillation frequency vs. ambient temperature 430 450 470 490 5 1 0 530 550 570 -50 -25 0 25 50 75 1 00 1 25 1 50 ambient temperature ta [ ] oscillation frequency [khz] vcc=3.3v,r t = 1 2k (fosc=500khz) regulated voltage vs. ambient temperature 2. 1 7 2. 1 8 2. 1 9 2.20 2.2 1 2.22 2.23 -50-250 255075 1 00 1 25 1 50 ambient temperature ta[ ] regulated voltage v reg [v] vcc=3.3v,r t = 1 2k (fosc=500khz) regulated voltage vs. load current 2. 1 7 2. 1 8 2. 1 9 2.20 2.2 1 2.22 2.23 0.0 0.2 0.4 0.6 0.8 1 .0 1 .2 load current i reg [ma] regulated voltage v reg [v] ta=-30 vcc=3.3v,r t = 1 2k (fosc=500khz) ta=25 ta=85 oscillation frequency vs.timing resistor 0 200 400 600 800 1 000 1 200 1 400 1 600 1 800 11 0 1 00 timing resistor r t [k ] oscillation frequency [khz] vcc=3.3v,ta=25 oscillation frequency vs. supply voltage vcc 490 492 494 496 498 500 502 504 506 508 5 1 0 05 1 0 1 520 vcc [v] oscillation frequency [khz] ta=25 ,r t = 1 2k (fosc=500khz) regulated voltage vs. supply voltage vcc 2. 1 7 2. 1 8 2. 1 9 2.20 2.2 1 2.22 2.23 05 1 0 1 520 vcc[v] regulated voltage v reg [v] ta=2 5 ,r t = 1 2k (fosc=500khz) load current i reg =0a
11 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V reference voltage vs. ambient temperature 0.980 0.985 0.990 0.995 1 .000 1 .005 1 .0 1 0 1 .0 1 5 1 .020 -50 -25 0 25 50 75 1 00 1 25 1 50 ambient temperature ta[ ] reference voltage v ref [v] vcc=3.3v,r t = 1 2k (fosc=500khz) error amp. output current(sink) vs. ambient temperature 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -50 -25 0 25 50 75 1 00 1 25 1 50 ambient temperature ta[ ] output current (sink) i sifb [ma] vcc=3.3v,r t = 1 2k (fosc=500khz) charge current of cp vs. ambient temperature -3.0 -2.5 -2.0 - 1 .5 - 1 .0 -50 -25 0 25 50 75 1 00 1 25 1 50 ambient temperature ta[ ] charge current of cp[ua] vcc=3.3v,r t = 1 2k (fosc=500khz) error amp. output current(source) vs. ambient temperature -350 -300 -250 -200 - 1 50 -50 -25 0 25 50 75 1 00 1 25 1 50 ambient temperature ta[ ] output current (source) i sofb [ua] vcc=3.3v,r t = 1 2k (fosc=500khz) threshold voltage of cp vs. ambient temperature 1 .5 1 .6 1 .7 1 .8 1 .9 2.0 2. 1 2.2 2.3 -50 -25 0 25 50 75 1 00 1 25 1 50 ambient temperature [ ] threshold voltage of cp [v] vcc=3.3v,r t = 1 2k (fosc=500khz) reference voltage vs. supply voltage vcc 0.980 0.985 0.990 0.995 1 .000 1 .005 1 .0 1 0 1 .0 1 5 1 .020 05 1 0 1 52025 vcc[v] reference voltage v ref [v] ta=2 5 ,r t = 1 2k (fosc=500khz)
12 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V output duty cycle vs.cs voltage (ch. 1 ) 0 1 0 20 30 40 50 60 70 80 90 1 00 0.80 0.90 1 .00 1 . 1 0 1 .20 1 .30 1 .40 1 .50 vcs 1 [v] output duty cycle (ch. 1 ) [ ] driving nch mosfet vcc=3.3v ta=25 fosc=300khz fosc=500khz fosc=760khz fosc= 1 .5mhz output duty cycle vs. oscillation frequency (ch. 1 ) 0 1 0 20 30 40 50 60 70 80 90 1 00 300 500 700 900 11 00 1 300 1 500 oscillation frequency [ ] output duty cycle (ch. 1 ) [ ] driving nch mosfet vcc=3.3v ta=25 vcs 1 =0.85v vcs 1 = 1 .35v vcs 1 =0.90v vcs 1 =0.95v vcs 1 = 1 .00v vcs 1 = 1 .05v vcs 1 = 1 . 1 0v vcs 1 = 1 . 1 5v vcs 1 = 1 .20v vcs 1 = 1 .25v vcs 1 = 1 .30v output duty cycle vs.cs voltage (ch. 1 ) 0 1 0 20 30 40 50 60 70 80 90 1 00 0.80 0.90 1 .00 1 . 1 0 1 .20 1 .30 1 .40 1 .50 vcs 1 [v] output duty cycle (ch. 1 ) [ ] driving pch mosfet vcc=3.3v ta=25 fosc=300khz fosc=500khz fosc=760khz fosc= 1 .5mhz output duty cycle vs. oscillation frequency (ch. 1 ) 0 1 0 20 30 40 50 60 70 80 90 1 00 300 500 700 900 11 00 1 300 1 500 oscillation frequency [khz] output duty cycle (ch. 1 ) [ ] driving pch mosfet vcc=3.3v ta=25 vcs 1 =0.85v vcs 1 = 1 .35v vcs 1 =0.90v vcs 1 =0.95v vcs 1 = 1 .00v vcs 1 = 1 .05v vcs 1 = 1 . 1 0v vcs 1 = 1 . 1 5v vcs 1 = 1 .20v vcs 1 = 1 .25v vcs 1 = 1 .30v
13 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V output duty cycle vs.cs voltage (ch.2) 0 1 0 20 30 40 50 60 70 80 90 1 00 0.70 0.80 0.90 1 .00 1 . 1 0 1 .20 1 .30 1 .40 vcs2 [v] output duty cycle (ch.2) [ ] driving nch mosfet vcc=3.3v ta=25 fosc=300khz fosc=500khz fosc=760khz fosc= 1 .5mhz output duty cycle vs. oscillation frequency (ch.2) 0 1 0 20 30 40 50 60 70 80 90 1 00 300 500 700 900 11 00 1 300 1 500 oscillation frequency [khz] output duty cycle (ch.2) [ ] driving nch mosfet vcc=3.3v ta=25 vcs2=0.85v vcs2=0.90v vcs2=0.95v vcs2= 1 .00v vcs2= 1 .05v vcs2= 1 . 1 0v vcs2= 1 . 1 5v vcs2= 1 .20v vcs2= 1 .25v vcs2= 1 .30v vcs2=0.80v output duty cycle vs. cs voltage (ch.2) 0 1 0 20 30 40 50 60 70 80 90 1 00 0.70 0.80 0.90 1 .00 1 . 1 0 1 .20 1 .30 1 .40 vcs2 [v] output duty cycle (ch.2) [ ] driving pch mosfet vcc=3.3v ta=25 fosc=300khz fosc=500khz fosc=760khz fosc= 1 .5mhz output duty cycle vs. oscillation frequency (ch.2) 0 1 0 20 30 40 50 60 70 80 90 1 00 300 500 700 900 11 00 1 300 1 500 oscillation frequency [khz] output duty cycle (ch.2) [ ] driving pch mosfet vcc=3.3v ta=2 5 vcs2=0.85v vcs2=0.90v vcs2=0.95v vcs2= 1 .00v vcs2= 1 .05v vcs2= 1 . 1 0v vcs2= 1 . 1 5v vcs2= 1 .20v vcs2= 1 .25v vcs2= 1 .30v vcs2=0.80v
14 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V out 1 terminal source current vs. h level output voltage -500 -450 -400 -350 -300 -250 -200 - 1 50 - 1 00 -50 0 0.0 1 .0 2.0 3.0 4.0 5.0 6.0 vcc-vout 1 [v] iout 1 [ma] vcc=2.5v vcc= 3v vcc= 5v vcc= 1 2v ta=2 5 out2 terminal source current vs. h level output voltage -500 -450 -400 -350 -300 -250 -200 - 1 50 - 1 00 -50 0 0.0 1 .0 2.0 3.0 4.0 5.0 vcc-vout2[v] iout2[ma] vcc=2.5v vcc= 3v vcc= 5v vcc= 1 2v ta=2 5 out 1 terminal source current vs. h level output voltage -300 -250 -200 - 1 50 - 1 00 -50 0 0.0 0.5 1 .0 1 .5 2.0 2.5 3.0 vcc-vout 1 [v] iout 1 [ma] vcc=3.3v ta=-30 ta=2 5 ta=8 5 out2 terminal source current vs. h level output voltage -300 -250 -200 - 1 50 - 1 00 -50 0 0.0 0.5 1 .0 1 .5 2.0 2.5 3.0 vcc-vout2[v] iout2[ma] vcc=3.3v ta=-30 ta=8 5 ta=2 5 out 1 terminal source currentvs. h level output voltage -500 -400 -300 -200 - 1 00 0 0.0 1 .0 2.0 3.0 4.0 5.0 vcc-vout 1 [v] iout 1 [ma] vcc= 1 2v ta=8 5 ta=-30 ta=2 5 out2 terminal source current vs. h level output voltage -500 -400 -300 -200 - 1 00 0 0.0 1 .0 2.0 3.0 4.0 5.0 vcc-vout2[v] iout2[ma] vcc= 1 2v ta=-30 ta=2 5 ta=8 5
15 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V out 1 terminal sink current vs. l level voltage 0 50 1 00 1 50 200 0.0 0.2 0.4 0.6 0.8 1 .0 1 .2 1 .4 vout 1 [v] iout 1 [ma] ta=-30 ta=25 ta=85 out2 terminal sink current vs. l level voltage 0 50 1 00 1 50 200 0.0 0.2 0.4 0.6 0.8 1 .0 1 .2 1 .4 vout2[v] iout2[ma] ta=-30 ta=85 ta=25 out 1 terminal rise time vs. supply voltage vcc 0 1 0 20 30 40 50 60 05 1 0 1 520 vcc[v] out 1 terminal rise time t rise [ns] ta=-30 c l = 1 000pf ta=25 ta=85 out2 terminal rise time vs. supply voltage vcc 0 1 0 20 30 40 50 60 05 1 0 1 520 vcc[v] out2 terminal rise time t rise [ns] ta=-30 c l = 1 000pf ta=25 ta=85 out 1 terminal fall time vs. supply voltage vcc 0 50 1 00 1 50 200 05 1 0 1 520 vcc[v] out 1 terminal fall time t fall [ns] ta=-30 c l = 1 000pf ta=25 ta=85 out2 terminal fall time vs. supply voltage vcc 0 50 1 00 1 50 200 05 1 0 1 520 vcc[v] out2 terminal fall time t fall [ns] c l = 1 000pf ta=85 ta=25 ta=-30
16 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V error amplifier gain and phase vs. frequency uvlo on threshold vs. ambient temperature 1 .8 1 .9 2.0 2. 1 2.2 2.3 2.4 2.5 -50 -25 0 25 50 75 1 00 1 25 1 50 ambient temperature ta[ ] uvlo on threshold v uvlo [v] operating mode supply current vs. oscillation frequency 2.0 3.0 4.0 5.0 6.0 300 500 700 900 11 00 1 300 1 500 oscillation frequency [khz] operating mode supply current i cca [ma] vcc=2.5v ta=2 5 vcc= 1 8v vcc= 1 2v vcc=5v vcc=3.3v cs 1 internal discharge switch current vs. voltage 0 50 1 00 1 50 200 250 300 350 400 0.00 0.50 1 .00 1 .50 2.00 2.50 vcs 1 [v] ics 1 off[ua] ta=-30 vcc=3.3v,rt= 1 2k (fosc=500khz) ta=25 ta=85 cs2 internal discharge switch current vs. voltage -200 - 1 50 - 1 00 -50 0 0.00 0.50 1 .00 1 .50 2.00 v reg -vcs2[v] ics2off[ua] vcc=3.3v,rt= 1 2k (fosc=500khz) ta=-30 ta=25 ta=85
17 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V 8. description of each circuit (1) reference voltage circuit (v ref ) this circuit generates the reference voltage of 1.00v 1% compensated in temperature from vcc voltage, and is connected to the non-inverting input of the error amplifier. the voltage cannot be observed directly because there is no external pin for this purpose. (2) regulated voltage circuit (v reg ) this circuit generates 2.20v 1% based on the reference voltage v ref , and is used as the power supply of the internal ic circuits. the voltage is generated when the supply voltage, vcc, is input. the v reg voltage is also used as a regulated power supply for soft start, maximum duty cycle limitation, and others. the output current for external circuit should be within 1ma. a capacitor connected between v reg pin and gnd pin is necessary to stabilize the vreg voltage (to determine capacitance, refer to recommended operating conditions). the v reg voltage is regulated in vcc voltage of 2.4v or above. (3) oscillator the oscillator generates a triangular waveform by charging and discharging the built-in capacitor. a desired oscillation frequency can be set by the value of the resistor connected to the rt pin (fig. 1). the built-in capacitor voltage oscillates between approximately 0.82v and 1.38v at fosc=500khz(that of ch1 and ch2 are slightly different) with almost the same charging and discharging gradients (fig. 2). you can set the desired oscillation frequency by changing the gradients using the resistor connected to the rt pin. (large rt: low frequency, small rt: high frequency) the oscillator waveform cannot be observed from the outside because a pin for this purpose is not provided. the rt pin voltage is approximately 1v dc in normal operation. the oscillator output is connected to the pwm comparator. (4) error amplifier circuit the error amplifier 1 has the inverting input of in1(-) pin (pin14). the non-inverting input is internally connected to the reference voltage v ref (1.00v 1%; 25 ). the error amplifier 2 has the inverting input in2(-) pin (pin4) and non-inverting input in2(+) pin (pin5) externally. since each input of error amplifier 2 is connected to the pins, ch2 is suitable for any circuit topology. the fb pins (pin3, pin15) are the output of the error amplifier. an external rc network is connected between fb pin and in- pin for gain and phase compensation setting. (fig. 3) for connecting of each topology, see design advice. ?
fig.1 r t value: small r t value: large 0.82v 1.38v fig.2 + ?? ? ? ? ?? ? ?
647
647 6<;? 6<; ? ???e ? ? y 9?47?? 9?47? fig.3
18 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V (5) pwm comparator the pwm output generates from the oscillator output, the error amplifier output (fb1, fb2) and cs voltage (cs1, cs2) (fig. 4). the oscillator output is compared with the preferred lower voltage between fb1 and cs1 for ch1. while the preferred voltage is lower than oscillator output, the pwm output is low. while the preferred voltage is higher than oscillator output, the pwm output is high. since the phase of ch2 is the opposite phase of ch1, higher voltage between fb2 and cs2 is preferred and while the preferred voltage is lower than the oscillator output, the pwm output 2 is high. (cannot be observed externally) the output polarity of out1, out2 changes according to the condition of sel pin. (see fig. 6) (6) soft start function this ic has a soft start function to protect dc-to-dc converter circuits from damage when starting operation. cs1 pin (pin10), and cs2 pin (pin7) are used for soft start function of ch1 and ch2 respectively. (fig. 5) when the supply voltage is applied to the vcc pin and uvlo is cancelled, capacitor c cs1 and c cs2 is charged by vreg through the resistor r7 or r9. therefore, cs1 voltage gradually increases and cs2 voltage gradually decreases. since cs1 and cs2 pin are connected to the pwm comparator internally, the pulses gradually widen and then the soft start function operates. (fig. 6) the maximum duty cycle can be set by using the cs pins. (see design advice about the detail) ??*/? +90=, ??*/? +90=, :*033(;6 9 6<;7<;
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647??
647? ?6<;7<;? ? ? ?y ?6<;7<; fig.4 ? ?
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fig.5 oscillator output cs1 pin voltage er.amp.1 output pwm output 1 out1 pch.drive (sel1 vreg) out1 nch.drive (sel1 gnd) oscillator output 2 pin voltage er.amp.2 output pwm output2 out2 pch.drive (sel2 vreg) out2 nch.drive (sel2 gnd) fig.6
19 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V (7) timer latch short-circuit protection circuit this ic has the timer latch short-circuit protection circuit. this circuit cuts off the output of all channels when the output voltage of dc-to-dc converter drops due to short circuit or overload. to set delay time for timer latch operation, a capacitor c cp should be connected to the cp pin (fig. 7). when one of the output voltage of the dc-to-dc converter drops due to short circuit or overload, the fb1 pin voltage increases up to around the vreg voltage for ch 1, or the fb2 pin voltage drops down to around 0 v for ch 2.when fb1 pin voltage exceeds 2.0v(max.) or fb2 pin voltage falls below 0.2v(min.), constant-current source (2 a typ.) starts charging the capacitor c cp connected to the cp pin. if the voltage of the cp pin exceeds 2.1 v (max.), the circuit regards the case as abnormal. then the ic is set to off latch mode and the output of all channels is shut off, (fig. 8) and the current consumption become 2ma(typ.) the period (tp) between the occurrence of short-circuit in the converter output and setting to off latch mode can be calculated by the following equation: cp thcptl cp i v c s tp * ] [ = v thcptl : cp pin latched mode threshold voltage [v] i cp : cp charge source current [ a] c cp : capacitance of cp pin capacitor you can reset off latched mode of the short-circuit protection by either of the following ways about 1) cp pin, or 2) vcc pin, or 3) cs1or cs2 pin: 1) cp voltage = 0v 2) vcc voltage uvlo voltage (2.2v, typ.) or below 3) set the cs pin of the cause of off latched mode as follows cs1 pin voltage = 0v, cs2 pin voltage = vreg if the timer-latched mode is not necessary, connect the cp pin to gnd. ?

*7 *7 fig.7 cp pin voltage [v] 1.0 2.0 time t start-up momentary short circuit short circuit short circuit protection tp 2.1v(max) vreg pin voltag fig.8
20 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V (8) output circuit the ic contains a push-pull output stage and can directly drive mosfets. the maximum peak current of the output stage is sink current of +150ma, and source current of - 400ma. the ic can also drive npn and pnp transistors. the maximum current in such cases is 50ma. you must design the output current considering the rating of power dissipation. (see design advice) you can switch the types of external discrete mosfets by wiring of the sel pins (pin 2, pin 16). for driving nch mos, connect the sel pins to gnd. for driving pch mos, connect the sel pins to vreg. you can design buck converter or inverting converter by driving pch mos, and boost converter by driving nch mos. connect them either to gnd or to vreg surely. (9) under voltage lockout circuit the ic contains a under voltage lockout circuit to protect the circuit from the damage caused by malfunctions when the supply voltage drops. when the supply voltage rises from 0v, the ic starts to operate at v cc of 2.2v(typ.) and outputs generate pulses. if a drop of the supply voltage occurs, it stops output at v cc of 2.1v(typ.). when it occurs, the cs1 pin is turned to low level and the cs2 pin to high level, and then these pins are reset.
21 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V 9. design advice (1) setting the oscillation frequency as described at section 8-(1), ?description of each circuit,? a desired oscillation frequency can be determined by the value of the resistor connected to the rt pin. when designing an oscillation frequency, you can set any frequency between 300khz and 1.5mhz. you can obtain the oscillation frequency from the characteristic curve ?oscillation frequency (fosc) vs. timing resistor resistance (r t )? or the value can be approximately calculated by the following expression. 16 . 1 86 . 0 4050 * 4050 ? ? ? ? ? ? ? ? = = ? fosc r r fosc t t this expression, however, can be used for rough calculation, the obitained value is not guaranteed. the operation frequency varies due to the conditions such as tolerance of the characteristics of the ics, influence of noises, or external discrete components. when determining the values, examine the effectiveness of the values in an actual circuit. the timing resistor r t should be wired to the gnd pin as shortly as possible because the rt pin is a high impedance pin and is easy affected by noises. (2) operation near the maximum or the minimum output duty cycle as described in ?output duty cycle vs. voltage?, the output duty cycle of this ic changes sharply near the minimum and the maximum output duty cycle. note that these phenom ena are conspicuous for high frequency operation (when the pulse width is narrow). (3) determining soft start period the period from the start of charging the capacitor c cs to widening n% of output duty cycle can be roughly calculated by the following expression: (see fig. 5 for symbols) ? ? ? ? ? ? ? ? = reg n cs cs v v c r ms t 1 1 1 ln * * 7 ] [ for cs1 pin ? ? ? ? ? ? ? = reg n cs cs v v c r ms t 2 2 ln * * 9 ] [ for cs2 pin c cs1 , c cs2 : capacitance connected to cs1or cs2 pin [ f] r7, r9: resistance connected to cs1 or cs2 pin [k ] v cs1n and v cs2n are the voltage of the cs1 and cs2 pins in n% of output duty cycle, and vary in accordance with operating frequency. the value can be obtained from the characteristic curve ?output duty cycle vs. cs voltage? to reset the soft start function, the supply voltage vcc is lowered below the uvlo voltage (2.1v typ.) and then the internal switch discharges the cs capacitor. the characteristics of the internal switch for discharge are shown in following the characteristics curves of ?characteristics of cs1 internal discharge switch current vs. voltage? and ?characteristics of cs2 internal discharge switch current vs. voltage?. therefore, when determining the period of soft start at restarting the power supply, consider the characteristics carefully. fosc: oscillation frequency [khz] r t : timing resistor [k ]
22 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V (4) setting maximum duty cycle as described in the fig. 9, you can limit maximum duty cycle by connecting a resistor divider "r7, r8 or r9, r10" between cs1, cs2 and vreg pin. set the maximum duty cycle considering that relation between the maximum output duty cycle and the cs pin voltage changes with operation frequency as described in the characteristics curves of ?output duty cycle vs. oscillation frequency? and ?output duty cycle vs. cs voltage?. when the maximum duty cycle is limited, cs pin voltage at start-up is described in fig. 10, and the approximate value of soft start period can be obtained by the following expressions: ? ? ? ? ? ? ? ? = 1 1 1 0 1 ln * * ] [ cs n cs cs v v c r ms t 8 7 8 * 7 0 r r r r r + = for cs1 the divided cs1 voltage is obtained by: reg cs v r r r v * 8 7 8 1 + = ? ? ? ? ? ? ? ? ? = 2 2 2 2 0 ln * * ] [ cs reg cs n cs cs v v v v c r ms t 10 9 10 * 9 0 r r r r r + = for cs2 the divided cs2 voltage is obtained by: reg cs v r r r v * 10 9 9 2 + = c cs1 , c cs2 : capacitance connected to the cs1 or cs2 pin [ f] r7, r8, r9, r10: resistance connected to cs1 or cs2 pin [k ] v cs1n and v cs2n are the voltages of cs1 and cs2 under a certain output duty cycle and varies with operation frequencies. the values of v cs1n and v cs2n can be obtained from the characteristics curve of ?output duty cycle vs. cs voltage?. the charging of c cs1 and c cs2 after uvlo is unlocked. therefore, the period from power-on of vcc to widening n% of output duty cycle is the sum of t0 and t ? ?
?

? t ? ? t
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fig.9 v cs1n reg v r8 r7 r8 ? + threshold voltage 0 v cc v cs2n reg v r 1 0 r9 r9 ? + v reg pin voltage 0 threshold voltage v cc fig.10 t0: time from power-on of vcc to reaching unlock voltage of uvlo
23 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V (5) determining the output voltage of dc-dc converters the ways to determine the output voltage of the dc- dc converter of each channel is shown in fig. 10 and the following equations. for ch1: the positive output voltage of dc-to-dc converter (a buck, a boost) is determined by: ref v r r r vout * 2 2 1 1 + = for ch2: the positive output voltage of dc-to-dc converter is determined by: 3 4 3 * 1 2 r r r v vout + = here, 6 5 6 * 1 r r r v v reg + = when r5=r6, ? ? ? ? ? ? + = 3 2 4 3 * 2 r r r v vout reg the negative output voltage of dc-to-dc converter (inverting) is determined by: reg v r r v r r r vout * 3 4 1 * 3 4 3 2 ? + = the ratio of resistances is determined by: 1 2 1 4 3 v vout v v r r reg + ? = (use the absolute value of the vout2 voltage.) when r5=r6, ? ? ? ? ? ? ? = 3 2 4 3 * 2 r r r v vout reg connect the sel1 and sel2 pin to gnd or vreg surely. (6) restriction of external discrete components and recommended operating conditions to achieve a stable operation of the ic, the value of external discrete components connected to vcc, vreg, cs, cp pins should be within the recommended operating conditions. and the voltage and the current applied to each pin should be also within the recommended operating conditions. if the pin voltage of out1, out2, or vreg becomes higher than the vcc pin voltage, the current flows from the pins to the vcc pin because parasitic three diode exist between the vcc pin and these pins. be careful not to allow this current to flow. ch1 ?? ? 6<;? ? ? ? 6<;? ?y ? ?? + ???e ?? ? 6<;? ? ? ? 6<;? ?y ? ?? + ???e buck boost ? ? ? 6<; ? y ? 6<; ? ? ? ? 6<; ? y ? 6<; ? ? ? ? 6<; ? y ? 6<; ? fig.11 buck boost inverting ch2
24 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V (5) loss calculation since it is difficult to measure ic loss directly, the calculation to obtain the approximate loss of the ic connected directly to a mosfet is described below. when the supply voltage is v cc , the current consumption of the ic is i cca , the total input gate charge of the driven mosfet is qg and the switching frequency is fsw, the total loss pd of the ic can be calculated by: pd P v cc *(i cca +qg*fsw). the value in this expression is influenced by the effects of the dependency of supply voltage, the characteristics of temperature, or the tolerance of parameter. therefore, evaluate the appropriateness of ic loss sufficiently considering the range of values of above parameters under all conditions. example) i cca =2.5ma for v cc =3.3v in the case of a typical ic from the characteristics curve. qg=6nc, fsw=500khz, the ic loss ?pd? is as follows. pd P 3.3*(2.5ma+6nc*500khz) P 18.2mw if two mosfets are driven under the same condition for 2 channels, pd is as follows: pd P 3.3*{2.5ma+2*(6nc*500khz)}=28.1mw
25 q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e q ualit y is our messa g e FA3687V FA3687V FA3687V FA3687V 10. application circuit ?2
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fb1 in1- in2- gnd in2+ fb2 rt cs1 cs2 sel1 cp vreg out1 vcc out2 sel2 FA3687V 15 14 11 10 12 13 9 16 45 3 2 1 7 6 8 ?2
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